A design based on the PCIe DMA transfer example design for Arria 10 device.

Hi @Sijith,

In the sub-design (Counter_FIFO_SignalTap.zip), it consists of only the counter and FIFO. The FIFO does not have the input signals (avalonmm_read_slave_address and avalonmm_read_slave_read) received from other IP. Based on the FIFO coding, in order to get the dataflow at FIFO output (avalonmm_read_slave_readdata) from the counter, it requires the trigger of input signals (avalonmm_read_slave_address and avalonmm_read_slave_read). When (avalonmm_read_slave_address == 0 and avalonmm_read_slave_read == 1), the readdata signal will get the data from the counter and hence there is dataflow at FIFO output. Otherwise, the readdata signal will not get the data from the counter, instead it will get {32(1’b0)}.

This also explains the observations of the Signal Tap result. The condition:

fifo_0_out_address = 0 and fifo_0_out_read = 1,

needs to be met to allow dataflow to happen when data_0_conduit_end_input is high. From the video recording, when you set the fifo_0_out_read to 1 or 0, you observed that no dataflow happened because the fifo_0_out_address is always set at 1.

In short, connect the avalonmm_read_slave_address and avalonmm_read_slave_read with valid signal if you have only counter + FIFO and want to check dataflow from counter to FIFO in the sub-design.

From the counter_fifo_signaltap.mp4 video, when sampled at a time instant, the fifo_0_out_readdata is observed to be different from the data_0_avalon_streaming_source data.

This is because the FIFO core performs the endian conversion to conform to the output interface protocol.

For instance, at 00:00:23 in the video, perform the endian conversion for fifo_o_out_readdata[31..0], you will get 00000000000000000000010100010010b, which is still not the same as the source_data, while the value is smaller than the source_data. Can you the add clock signal that drives the source_data and fifo_o_out_readdata, and the signals that carry the data before passing it to the fifo_o_out_readdata signal in the Signal Tap to check that the correct data are passed to fifo_o_out_readdata?

Next, the Signal Tap logic analyzer is used as a debugging tool to capture and store the specific signal data continuously when the trigger conditions set are met. User only specify conditions that trigger the start or stop of data capture. Therefore, assigning variables in Signal Tap is not possible. Assigning variables should be done in the coding.

Besides, did you compile successfully on the original PCIe DMA transfer example design without adding Signal Tap?

There is a similar issue discussed in the Intel Community Forum. Can you check out the forum thread? https://community.intel.com/t5/Intel-Quartus-Prime-Software/3-Wire-SPI-IP-Component-with-Arria-10/m-p/1476199/highlight/true

Thanks.

Best Regards,

VenTing_Intel