A design based on the PCIe DMA transfer example design for Arria 10 device.

Sure! it would be great if you could have a look into my design (the signal connection of the Counter FIFO to the PCIe DMA example design) to make sure the connections makes sense (pls see png files attached to the link in my first message). If not any suggestions to improve it is highly appreciated. (FYI: What I really want is stream the data generated in the counter (which on/off with an external switch) through a FIFO (Intel Avalon MM FIFO IP, with streaming input and MM-output that I have used) then the data should go to the PCIe DMA transfer example design and the data written in DDR4 element then should read from the host computer through API functions provided)

Also, I have tried run example design and it was running fine that time.