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Altera_Forum
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15 years ago

A bug of LUT component?

Platform: xp + dsp builder 9.1 sp2 + matlab R2010a The LUT component works well in simulink. When I generate VHDL files and use them in Quartus, its instance outputs only the first value, but ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

i've seen this or something similar before. i'm fairly certain its fixed in newer versions

try using the ROM block instead of the LUT. i don't think it had that problem

i think the problem has to do with the output register of the LUT. try disabling it and using an external delay if the ROM doesn't work

for future reference i think a couple of other blocks had problems with the output register so if your hardware doesn't match Simulink either update to recent software or take a look at post-fit netlists to see if you can see the register disappearing