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Honored Contributor88E1111 Marvell PHY Chip Clock
Hi Friends.
This post is about Marvell 88E1111. It's close to impossible getting any information from them. On connecting the 25MHz crystal to the XTAL1 and XTAL2, does the chip internally generate 125MHz? There's an output pin 125CLK. Can this be used by my IP as the TxCLK? Your advise would be helpful to me. Thanks.14 Replies
Altera_ForumThere are lots of ways to connect the 88E1111. The Terasic DE2-115 dev board uses it. Check the DE2-115 schematic and the Ethernet demos for how it is used on this board. In this design 125CLK is not connected. The transmit clock is the TX_CLK pin. The chip is fed an externally generated 25 MHZ clock in to the XTAL1 pin.
It is possible to get technical info on Marvell products. You need to go through a distributor and sign a NDA. I wouldn't recommend doing an original design with the 88E1111 unless you do this so you can have the documentation available.- Altera_Forum
Thanks for your reply Galfonz. I will try it.
Nitrogen - Altera_Forum
Hello,
I hope that someone faced a similar problem. I'm trying to implement FPGA and PC communications using Nios II Stratix II edition, Etnernet PHY daughter board with the Marvell 88E1111 and TSE MAC. I read TSE user guide from start to the end, initialized registers MAC and Phy, created frame generator. The initial task is to send ARP packet and UDP packet on the PC. During the development I have encountered such a problem: to the transfer of the ARP request packet normally comes to the computer and the computer also reply to FPGA, but when I'm trying sent UDP packet Transmit LED at PHy blinks, but there are nothing at PC side. (I monitoring ethernet traffic with WireShark soft). When i send UDP packet with wrong destination MAC adress this packet shown at Wireshark, but if i use correct destination MAC, wireshark monitor show nothing. At PC side, however incoming and sending bytes at Ethernet connection window are correct. In addition, there is another problem: receive path at Phy is "dead", TSE receive work fine (i checked it with loopback), but line between MAC and Phy is silent. When Ethernet cable connected PC start sending at network different frames, Phy receive LED blink and in theory i should see them at MII line between MAC and Phy (with the help of signaltap analyzer). But there is nothing. Can anybody help me with this problem? PS. Sory for my bad English =) - Altera_Forum
Verify that the PHI has the MAC address configured correctly. If it thinks the MAC address is different from that on the packet you are sending the PHI won't send it to the FPGA. Get hold of the 88E1111 documentation and verify you can read some of its registers. Read back the MAC address.
I would run the example code and FPGA configuration that came with your Ethernet daughter board. If that works, try building it from source and verify that you can create a working configuration. Use the same Quartus version as the example was built with to start. If that works you can work up to newer versions. - Altera_Forum
Thanks for reply,
Can you tell me at what register Phy usually contain MAC address. Because there are only based MDIO registers at Reference guide from Altera site, and thats only documentation i have about that Phy. Or can I just read extended registers from MDIO and hoped to find a MAC address of Phy? - Altera_Forum
That info is covered in the Marvel documentation. It's under an NDA (non disclosure agreement) so I can't tell you. Check the Ethernet standards documents, I think there is a set of common registers that all PHYs support. Also, look at the source code for drivers that use the 88E1111.
- Altera_Forum
Well, after new experiments I solve some of my problems) I understand that I was use signaltap analyser with wrong trigger configuration. Thats why I see nothing at receive path. After configurating triggers, I was convinced that Phy recieve all packets at Ethernet line and send it to TSE MAC.
So this is great! But there are still some problems with transmit UDP packets. Wireshark at my PC correctly capture at Ethernet line any UDP packets from FPGA with destination MAC - different than MAC of my PC network card. UDP frame with broadcast destination MAC appears at Wireshark. But when I set as destination MAC from my PC, Phy transmit LED Blinking, Signaltap show at MII line correct frame, but Wireshark show nothing (I tried to capture traffic with CommView, but its all the same). UDP with correct destination MAC missing. So I don`t understand how this can be, I suppose that I missing something importatnt, but I don`t know what =(. - Altera_Forum
Do you see the RX light on the PC? If not, then the Ethernet packet is somehow malformed. Check your transmitted Ethernet and UDP headers, the Ethernet packet checksum and UDP packet data checksum. If you don't see the RX light, I'd suspect the Enet header or checksum. Note that you can't rule out malformed Ethernet packets if you see the light. Some PCs blink the light even if malformed packets are sent. If your packets are malformed, they may be discarded by the OS before being sent to wireshark.
Also, make sure you have Wireshark set the interface to promiscuous mode. - Altera_Forum
Thanks for your help!
Transmit is working properly. I tried to Use WinDump instead of Wireshark, and it show transmitting UDP packets, and also it said that IP header length mismatch with true length of packet. So I made a mistake at forming IP header. When I correct IP header, Wireshark start capturing UDP packet and UDP receiver at PC start to receive it. Well, thanks again for your advice! - Altera_Forum
Hi,
I am new with Altera De2-115 board. I saw there is two marvell PHY chip in DE2-115 board. My plan is used both. One for receiving data and other one for transmitting. But I don't know how to identify them first. Second I dont know how to interface the chip to FPGA? I can see that i have to use MDIO in order to do some configuration in PHY chip registers. Would someone help me please where to start? Thanks in advance
