88E1111 Marvell PHY Chip Clock

Hello,

I hope that someone faced a similar problem. I'm trying to implement FPGA and PC communications using Nios II Stratix II edition, Etnernet PHY daughter board with the Marvell 88E1111 and TSE MAC. I read TSE user guide from start to the end, initialized registers MAC and Phy, created frame generator. The initial task is to send ARP packet and UDP packet on the PC. During the development I have encountered such a problem: to the transfer of the ARP request packet normally comes to the computer and the computer also reply to FPGA, but when I'm trying sent UDP packet Transmit LED at PHy blinks, but there are nothing at PC side. (I monitoring ethernet traffic with WireShark soft). When i send UDP packet with wrong destination MAC adress this packet shown at Wireshark, but if i use correct destination MAC, wireshark monitor show nothing.

At PC side, however incoming and sending bytes at Ethernet connection window are correct.

In addition, there is another problem: receive path at Phy is "dead", TSE receive work fine (i checked it with loopback), but line between MAC and Phy is silent. When Ethernet cable connected PC start sending at network different frames, Phy receive LED blink and in theory i should see them at MII line between MAC and Phy (with the help of signaltap analyzer). But there is nothing.

Can anybody help me with this problem?

PS. Sory for my bad English =)