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A look at what SignalTap picks up before and after the DMA module shows that all 64 bits are read from the memory, but only the lowest 32 bits of this data makes it to the component with the upper 32 bits being set to zero.
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I don't have a direct answer to your problem, but I wanted to mention that since you're already setup with SignalTap, what you actually want to look at is the Avalon-MM Master port from the DMA and then the Slave port within your component. In other words, the before/after of all the Qsys-generated connections including any adapters it inserted. You can also figure this out by skimming the generated code, but in your case maybe it's faster to just examine it live.
If you see the DMA posting a properly formed 64-bit write, but your component only sees the 32-bit write, you know the issue is with how Qsys perceives your component (byteenables or otherwise) and the issue is not with your register settings for the DMA.
Honored Contributor
