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Altera_Forum
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16 years ago

3G-SDI IO standard and pin locking

Hi, I am trying to do pinlocking for 3G-SDI(tripple rate), what are the standards should i set for refrence clock and differential serial data? when i try to pin lock the differential refrence ...
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Altera_Forum
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16 years ago

1 - Let the Pin Planner assign complementary pins for differential interfaces.

2 - You will have problems if you assign transceiver pins (including reference clocks) but they are not connected to anything in your design. For example, the error you mentioned above could be due to the fact that you declared the pin in your design, you've given it a pin assignment, but it's not used for anything.

3 - The differential serial outputs use the 1.5V PCML standard.

4 - The differential serial inputs can use CML, LVPECL, or LVDS (see table 1-4 in the handbook)

http://www.altera.com/literature/hb/arria-ii-gx/aiigx_5v2.pdf

5 - Table 2-1 shows the supported standards for the reference clocks (same as receivers).

Jake