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Honored Contributor
Honored Contributor125MHz PCIe application clock on a large cyclone V
We are trying to get a large Avalon bus based design to pass timing using the 125MHz clock from the PCIe block. The design passed at 62.5MHz (just), but we want to use more than PCIe 1.0 x1 - whic...
Altera_ForumHonored Contributor
Honored ContributorI've read those bits.
Setting "Limit interconnect pipeline" to 1 actually makes things worse. While I'm not worried about the performance of the BAR masters, I don't want to add a lot of extra clocks to some other master-slave pairs. One 'problem' signal seems to be the waitrequest signal that is generated when the arbiter finds the slave busy. I think that needs a 'non-pipelined' bridge that always asserts waitrequest for one cycle.
