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Honored Contributor
Honored Contributor125MHz PCIe application clock on a large cyclone V
We are trying to get a large Avalon bus based design to pass timing using the 125MHz clock from the PCIe block. The design passed at 62.5MHz (just), but we want to use more than PCIe 1.0 x1 - whic...
Altera_ForumHonored Contributor
Honored ContributorI think "Limit interconnect pipeline" might be the parameter you can tweak and possibly see an improvement.
https://www.altera.com/en_us/pdfs/literature/hb/qts/qts-qps-5v1.pdf Search for "Limit interconnect pipeline" and you'll find a couple paragraphs in different sections for tweaking that parameter, which might be all you need to put this topic behind you.
