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Altera_Forum's avatar
Altera_Forum
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9 years ago

125MHz PCIe application clock on a large cyclone V

We are trying to get a large Avalon bus based design to pass timing using the 125MHz clock from the PCIe block. The design passed at 62.5MHz (just), but we want to use more than PCIe 1.0 x1 - whic...
Altera_Forum's avatar
Altera_Forum
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9 years ago

Avalon "goop" happens whenever you've got dissimilar masters/slaves. Whenever possible, I try to put a Clock Crossing bridge whenever the bus width or clock domain changes, and a Pipeline Bridge anywhere anything else [bursting] changes.

So from your description, I'd at least try a configuration like:

(BAR master) -> (Avalon-MM Clock Crossing Bridge [x64]) -> (Avalon-MM Pipeline Bridge x32 non-bursting) -> (your slaves)

(your slaves) -> (Avalon-MM Clock Crossing Bridge) -> PCIe ports.

If you really don't care about performance, I'd consider using the clock crossing bridge to put your slaves in a different clock domain if possible.

Another thing to consider is that if you've just plain got too many nodes connecting to the same arbiter / "goop", split up your buses with Pipeline Bridges possibly in a tree topology.