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Altera_Forum
Honored Contributor
Honored Contributor10g mac - avalon_st_tx_ready de-asserted in the middle of the packet transfer
Hi All, Does anybody know why avalon_st_tx_ready de-asserted in the middle of the packet transfer? Attached a capture of signal tap. I can see a missing data on the pc that receive this ...
Altera_ForumHonored Contributor
Honored ContributorIn Signal Tap : the packets are transmited by an external PC (was validate and works fine).
In simuation : the same packets are transmited by a test bench. The fpga logic is ALTERA's IPs (MAC & PHY). no logic was added. Do you think altera has problem with this IP?
