Forum Discussion
Altera_Forum
Honored Contributor
10 years ago10g mac - avalon_st_tx_ready de-asserted in the middle of the packet transfer
Hi All, Does anybody know why avalon_st_tx_ready de-asserted in the middle of the packet transfer? Attached a capture of signal tap. I can see a missing data on the pc that receive this ...
Altera_Forum
Honored Contributor
10 years agobetter picture with more signals:
At the top of the picture you can see the data comes in the fpga (from pc) At the bottom of the picture you can see the data transmited from the fpga to the output(to pc).