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Altera_Forum
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10 years ago

10g mac - avalon_st_tx_ready de-asserted in the middle of the packet transfer

Hi All, Does anybody know why avalon_st_tx_ready de-asserted in the middle of the packet transfer? Attached a capture of signal tap. I can see a missing data on the pc that receive this ...
Altera_Forum's avatar
Altera_Forum
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10 years ago

If the ready latency = 0, what does the data change when ready is low?

The length of the package from the (very low resolution) picture you sent appears to show 15 transactions, when a 124 byte package would require 16 transactions with tx_empty set when end of packet is asserted.

Please post a better picture with more signals

Next question - did you simulate this design before putting it in the FPGA?