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Altera_Forum
Honored Contributor
Honored Contributor10G-BASER PHY High bit error rate
Hi All, I am trying to bring up 10 GBASER PHY in Stratix V FPGA. After setting up the Design based on the reference design provided I am still having trouble with my hi_ber signal. It still remain...
Altera_ForumHonored Contributor
Honored ContributorHello Sir,
do you set good assigment to?: XCVR_TX_SLEW_RATE_CTRL XCVR_TX_PRE_EMP_1ST_POST_TAP XCVR_TX_VOD OUTPUT_TERMINATION INPUT_TERMINATION XCVR_RX_LINEAR_EQUALIZER_CONTROL INPUT_TERMINATION ?
