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AGU
New Contributor
New Contributor.vho to verilog
There is a .vho file generated from the file tap_top.v. The file tap_top is used for simulating the HARD IP SEU (Single Event Upset).
In a previous project a .vho is available which is different f...
AGUNew Contributor
New ContributorHi John,
thank you for the answer.
Is there a tap_top with the following entity?
ENTITY tap_top IS
PORT (
tdo_pad_o : OUT std_logic;
tdo_padoe_o : OUT std_logic;
shift_dr_o : OUT std_logic;
pause_dr_o : OUT std_logic;
update_dr_o : OUT std_logic;
capture_dr_o : OUT std_logic;
crc_select_o : OUT std_logic;
crc_err : OUT std_logic;
fpga_err : OUT std_logic;
dr_reg2_ext : OUT std_logic_vector(31 DOWNTO 0);
rst : IN std_logic;
tms_pad_i : IN std_logic;
tck_pad_i : IN std_logic;
trst_pad_i : IN std_logic;
tdi_pad_i : IN std_logic;
crc_test_active : IN std_logic;
crc_test_active_n : IN std_logic
);
END tap_top;
