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Altera_Forum
Honored Contributor
Honored Contributorzeroing of sampled signal : how ?
in my series of "stupid beginner questions" I hit a new problem.
My ADC samples a signal. however, it is not guaranteed that 0 volts is reported as 128. it might be 115 or 130. correcting this is easy : just add/subtract some value until the mean is 128. (so you can scale/multiply the signal maximally) But how do I determine the mean reliably in my cosy little FPGA? how does the rest of the world solve this challenge ? is everybody twiddling analog potmeters to get the input signal just right ? please tell me the clever solution :-P...6 Replies
Altera_ForumA nasty project delay occurred called holidays :-P
back next weekend- Altera_Forum
good point. did you find relevant threads?
- Altera_Forum
thanks again !
The secret of it all is in knowing the right search terms :-P.... - Altera_Forum
and finally...
there are threads that talk about DC offset elsewhere on the forum. some good reading if i recall correctly - Altera_Forum
you could do some kind of neat calibration circle where the FPGA grounds the input, samples the offset, latches the value, and then samples the input signal and subtracts the offset. this would have the advantage of not being a HPF
note that you're losing headroom in your ADC when you're sampling DC offset - Altera_Forum
i usually don't care about DC so i use a simple recursive filter with a zero at DC and a pole just barely inside the unit circle
something like: H(z)=(z-1)/(z-0.999)
