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Altera_Forum's avatar
Altera_Forum
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14 years ago

zeroing of sampled signal : how ?

in my series of "stupid beginner questions" I hit a new problem. My ADC samples a signal. however, it is not guaranteed that 0 volts is reported as 128. it might be 115 or 130. correcting ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

you could do some kind of neat calibration circle where the FPGA grounds the input, samples the offset, latches the value, and then samples the input signal and subtracts the offset. this would have the advantage of not being a HPF

note that you're losing headroom in your ADC when you're sampling DC offset