Honored Contributor
Honored ContributorI use both Xilinx and Altera. From a user point of view the big difference with Altera is that you just don't concern yourself with intermediate generated files. The only generated files I generally concern myself with are:
1 - files generated by the IP cores. These are normally just generated Verilog or VHDL files and constraint files (SDC files). 2 - Programming files (SOF,POF, RBF); similar to the .BIT files that ISE gives. 3 - The Quartus settings file (QSF) which contains all the settings for the project. 4 - If you are using SoPC builder (Altera's version of EDK), then you also want to keep track of the .sopcinfo file. My personal opinion is that it's quite nice. Particularly regarding the IP cores. For example, try generating a simple RAM block in ISE with CoreGen and you get this mountain of useless files. With Quartus, you get one file and it's Verilog (or VHDL). You just include that one file as part of your design and you're done. If you really want something like a comparison between the two tool flows, try this: http://www.altera.com/products/software/switching/ise/ise-designers.html Jake
