Occasional Contributor
Occasional ContributorHi David,
It seems your incident is closed (apologies for that) but let me assure you that I'll be continuing to assist you within this thread.
Regards,
Harsh M
Occasional ContributorHello Harsh,
Some screenshots as follows:
1. jesd_toolkit_setup: shows that I have enabled the toolkit in Platform Designer
2. from_system_console: shows that the JTAG master is recognized
3. no_XCVR_toolkit_available: however no toolkit is available
Basically the flow is:
1. Program the SOF
2. Use ISSP Source to trigger a module within FPGA that configures the clock generator on the board to start making clocks
3. Use System Console to configure the ADC (JESD mode, PLL etc)
4. Program the SOF again. This is to ensure that the FPGA exits it's configuration phase when the input transceiver reference clock and JESD lanes are active
5. check SYNC_N from JESD IP (always low)
6. reset JESD IP
7. check SYNC_N from JESD IP (always low)
That's it.
Any help appreciated.
David
