Xcievers communication between Cyclon10gx to Agillex F Tile FGT PMA direct

Hello,

In our application we are designing a Xcievers link between cyclon10GX device (10CX150YF672E6G) to a intel Agillex F-TILE (AGFB027R24C2E2VR0 )

On the Cyclone side we use PCS where in the alignment section we use " automatic synchronization state machine " . also the bit slip is disabled.

on the Agilex just use the direct PMA FGT .

Design Rate is 2Gbps.

I have concern regarding the alignment issue between the 2 FPGA's.

The PCS option tab (seen on the cyclon10gx) is not seen on the Agillx FGT settings , so

Is there any known issue that prevents this communication alignments ?

Can you guide for the right settings for it to work on both sides ?

We understand the 8b/10b encoding need to be added by soft code on the Agillex side.

Thanks,

Avichay