X state trace

Hi,

I met a problem when I simulate to a design.

when do function simulation, all good.

when do timing simulation ( vho + sdo ), there are some 'X' in data out bus. see attached picture "3.jpg". I then try to trace where "X" come from. I found it is caused by a line, see attached "2.jpg". But I don't know how to solve this. Is this caused by path delay?

Could somebody help me?

Thanks in advance.