Writing and Reading Data To & From RAM

Hi,

I am trying to create a RAM (which is of 32*4 size) using the Mega Wizard Plug In Manager. So there are 32 rows into which data of 4 bits long can be written. The initialisation of the RAM is successful. Now, in order to fill the data into the RAM's locations one after the other, I have created an FSM which has a counter running from 0 to 31. The counter value is the address of the RAM. Thereby data is written onto the locations of the RAM.

When i simulate this program on the software, I get proper results. But when I try to run this program on the FPGA, I need to change the input and output variables such as data, input and output to SW[3:0], LEDG, LEDR etc. After changing like this, I am getting errors on the Software. When I try to mend the errors and run the program on FPGA the output does not come correctly on the FPGA. So I try to write a single bit into each location into the RAM but in vain again. I have tried all kinds of tweaking but FPGA still does not recognise the RAM. The code for the program is:

module ram (SW,LEDG,LEDR,clock);

input clock;

input [9:0] SW;

output [9:0] LEDR;

output [7:0] LEDG;

`ifndef ALTERA_RESERVED_QIS

// synopsys translate_off

`endif

reg GrOp;

integer wraddress;

integer rdaddress;

wire FSMW, wre;

assign FSMW = SW[7];

assign wre = FSMW ;

reg Ready1;

reg [3:0] out;

initial

begin

out = 4'b0000;

rdaddress = 4'b0000;

wraddress = 4'b0000;

end

always @ (posedge clock)

begin

Ready1 = 1'b0;

wraddress <= out; // wraddress <= out;

rdaddress <= out;

Ready1 = 1'b1;

out = out + 1;

GrOp = Ready1;

end

assign LEDG = GrOp;

`ifndef ALTERA_RESERVED_QIS

// synopsys translate_on

`endif

wire [3:0] sub_wire0;

wire [9:0] LEDR = sub_wire0/*[3:0]*/;

altsyncram altsyncram_component (

.wren_a (wre), // SW[5]

.clock0 (clock),

.address_a (wraddress),

.address_b (rdaddress),

.data_a (SW), //.data_a ([3:0] SW),

.q_b (sub_wire0),

.aclr0 (1'b0),

.aclr1 (1'b0),

.addressstall_a (1'b0),

.addressstall_b (1'b0),

.byteena_a (1'b1),

.byteena_b (1'b1),

.clock1 (1'b1),

.clocken0 (1'b1),

.clocken1 (1'b1),

.clocken2 (1'b1),

.clocken3 (1'b1),

.data_b ({4{1'b1}}),

.eccstatus (),

.q_a (),

.rden_a (1'b1),

.rden_b (1'b1),

.wren_b (1'b0));

defparam

altsyncram_component.address_reg_b = "CLOCK0",

altsyncram_component.clock_enable_input_a = "BYPASS",

altsyncram_component.clock_enable_input_b = "BYPASS",

altsyncram_component.clock_enable_output_a = "BYPASS",

altsyncram_component.clock_enable_output_b = "BYPASS",

altsyncram_component.intended_device_family = "Cyclone II",

altsyncram_component.lpm_type = "altsyncram",

altsyncram_component.numwords_a = 16,

altsyncram_component.numwords_b = 16,

altsyncram_component.operation_mode = "DUAL_PORT",

altsyncram_component.outdata_aclr_b = "NONE",

altsyncram_component.outdata_reg_b = "UNREGISTERED",

altsyncram_component.power_up_uninitialized = "FALSE",

altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",

altsyncram_component.widthad_a = 4,

altsyncram_component.widthad_b = 4,

altsyncram_component.width_a = 4,

altsyncram_component.width_b = 4,

altsyncram_component.width_byteena_a = 1;

endmodule

Please let me know how to overcome this problem in Altera FPGA.