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Altera_Forum
Honored Contributor
15 years agoThanks for the reply, JacoL. I checked the RTL schematic of the code on Quartus. rden_a & rden_b pins are both at logical 1 by default. The Quartus software I use does not have a signaltap feature.
I have some other programs (for eg adder) on FPGA...they have all worked fine. Only this RAM program doesn't work. The FPGA does not recognise the format of the program somehow.