Forum Discussion
Altera_Forum
Honored Contributor
11 years agoHi,
if you use the General control signals DEVn and OEn, tying them to GND would enable the Output and clear the I/O, thus any pin would be at least in a defined Level. If you do not use These Pins, I think at least OEn should be tied to GND, but that maybe my personal habbit. The small current - tying the signals to GND with the weak pull - will be very small compared by the normal Operation current the design will consume. The CLK Signals however feed a dedicated clock routing network, thus these are internal routes running across the complete chip and would spread any noise picked up also across the complete chip. thus it is a good idea to take care of the unused clock network lines to be connected to GND. If you do not intend to use the not connected clock lines, you may connect both together with a pull-down to GND. Kind regards :-)