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ETheo3
New Contributor
New ContributorWhy would always @ (posedge) execute when no clock edge occurs?
I have a simple verilog program that uses an always loop: wire clk_pwm; reg out_4; reg [1:0] cnt_b; always_ff @ (posedge clk_pwm) begin cnt_b <= cnt_b + 1; if (out_4 == 0)...
ETheo3New Contributor
New ContributorI'll answer my own question:
The 'extra' hits in the always loop were from glitches in the clock, creating extra posedges. I wasn't seeing the edges on the outputs because they were to fast to show up on the logic analyzer. (Faster than the sampling rate.)
The solution was to debounce the generated clock signal to get rid of the glitches.
