Why would always @ (posedge) execute when no clock edge occurs?

I have a simple verilog program that uses an always loop:

wire clk_pwm;

reg out_4;

reg [1:0] cnt_b;

always_ff @ (posedge clk_pwm)

begin

cnt_b <= cnt_b + 1;

if (out_4 == 0) out_4 <= 1;

else out_4 <= 0;

end

I'm outputting the 2 bit cnt_b, clk_pwm, and out_4 onto I/o pins.

On the output pins I'm seeing out_4 toggle and cnt_b increment when no edge occurs on clk_pwm!

What could cause something like this to happen?

Thanks for any help.