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Altera_Forum's avatar
Altera_Forum
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15 years ago

Why does the Parallel Flash Loader (PFL) fail to configure my FPGA after programing f

use PFL (in MAX II device) configure FPGA.Based on an386.pof,I found Quartus programmer can erase and program flash using pfl. However,after programing flash, pfl fails to configure FPGA. The config_done pin of FPGA is always low, and nconfig pin of FPGA is a pulse. It looks like the pfl is always configure FPGA, and FPGA can't drive the config_done pin high. what is the reason?

When using pfl, I select 64M CFI, actually the flash is 512M. Does it have some bad influence?

I alwayes drive pfl_nreset pin and pfl_flash_access_granted pin high, which makes pfl alwayes configure FPGA? Or I should drive pfl_nreset pin low after configuring FPGA?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    The size of CFI specified in PFL must be same as the actual flash size or bigger. Change the settings and try again to see if the problem still occurs. The rule: actual flash must be less than or equal to size specified in PFL