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Altera_Forum
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11 years ago

Why does my code not like the addition clock in to the always loop?

Hi,

This is my very simple code. If i have a single clock going in to the always loop, i get very few warnings and when i simulate it, i get an output. If i add a second clock in to the always loop, as shown here. I don't get any errors but for some reason it doesn't like it and i don't get anything out. I do quite quite of few extra warnings.

The clocks are generated by a PLL. I have a 50Mhz clock going in to the PLL and output 2 300Mhz outputs that are 180 degrees out of phase of each other. I'm using a Cyclone III EP3C25F324. 

module Pulse(input clk,
input clk2, 
output reg out,
output reg state_var,   //debug outputs
output reg counter);
parameter 	init	= 4'd0,
						run = 4'd1;
initial
	begin
		state_var<=init; //Straight in to Init
	end
	always @(posedge clk or posedge clk2)
			begin
			case (state_var)
			init:	begin
                                                counter = 3'd0;
						state_var <= run;
			end
					
			run: begin									
						if (counter == 2'd0)
						begin
								out<= 1'b1;
						end
						
						if (counter == 2'd1) //50% duty cycle
						begin
								out<= 1'b0;
						end
												
						
						if (counter == 2'd1) //Restart at 50% duty cycle
						begin
								counter <= 2'd0;
						end
						else
						begin
						counter <= counter + 1'b1;
						end
						
			end
			endcase
		end
endmodule

Thanks

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Even of you do stimulate it, the problem will be synthesis. Registers in an fpga can only be clicked from a single clock. Also 300 mhz is about the limit of a cyclone.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    What do you mean by the registers can only be clicked from a single clock? Are you referring to the always loop being entered or are you meaning the values within the registers can only be updated with one clock?

    I thought that the always blocks would be entered when a new 'event' occurred. So when either clock has a rising edge, this would trigger the always block to run. I don't particularly see the difference between 2 clock inputs and 2 other inputs where the data is flowing in just as fast. I do know that verilog describes hardware - some times i just find it easier to talk about it as if it was software.

    I backed off the PLL so they outputted 20Mhz each, which 40Mhz is no where near the Max frequency. I still didn't get anything out of it. I thought this would have worked. How do people manage to obtain DDR operation?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    In verilog, you are right, the always block will always be entered when you get an event on clk or clk2:

    always @(posedge clk or posedge clk2)

    So it's perfectly legal Verilog. The problem is it will not map to anything on an FPGA, as they can only accept a single clock per register. Your code has to be translated to real hardware, so you need to bare this in mind.

    I suggest you output a 40MHz clock from your PLL