Why does my code not like the addition clock in to the always loop?

What do you mean by the registers can only be clicked from a single clock? Are you referring to the always loop being entered or are you meaning the values within the registers can only be updated with one clock?

I thought that the always blocks would be entered when a new 'event' occurred. So when either clock has a rising edge, this would trigger the always block to run. I don't particularly see the difference between 2 clock inputs and 2 other inputs where the data is flowing in just as fast. I do know that verilog describes hardware - some times i just find it easier to talk about it as if it was software.

I backed off the PLL so they outputted 20Mhz each, which 40Mhz is no where near the Max frequency. I still didn't get anything out of it. I thought this would have worked. How do people manage to obtain DDR operation?