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Altera_Forum
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11 years ago

Why does my code not like the addition clock in to the always loop?

Hi, This is my very simple code. If i have a single clock going in to the always loop, i get very few warnings and when i simulate it, i get an output. If i add a second clock in to the always ...
Altera_Forum's avatar
Altera_Forum
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11 years ago

In verilog, you are right, the always block will always be entered when you get an event on clk or clk2:

always @(posedge clk or posedge clk2)

So it's perfectly legal Verilog. The problem is it will not map to anything on an FPGA, as they can only accept a single clock per register. Your code has to be translated to real hardware, so you need to bare this in mind.

I suggest you output a 40MHz clock from your PLL