Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Why does my code not like the addition clock in to the always loop?

Hi, This is my very simple code. If i have a single clock going in to the always loop, i get very few warnings and when i simulate it, i get an output. If i add a second clock in to the always ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Even of you do stimulate it, the problem will be synthesis. Registers in an fpga can only be clicked from a single clock. Also 300 mhz is about the limit of a cyclone.