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student8's avatar
student8
Icon for New Contributor rankNew Contributor
2 years ago

Why does fitting fail when there are still resources available?

Layout and routing resources are still available, but layout fails. The Quartus error is as follows: Error (170143): Final fitting attempt was unsuccessful Info (170138): Failed to route the...
Board Debug
Configuration
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,
fitting failure with a rather low resource utilisation indicates that your design sets special constraints that can't be fulfilled by Quartus. Can be e.g. incompatible location assignments or WYSIWYG primitives.

Unlikely to happen in regular design.

  • student8's avatar
    student8
    Icon for New Contributor rankNew Contributor
    2 years ago

    Thank you for your response. I am debugging an FPGA chip embedded in a fixed development board, and I cannot arbitrarily change pin assignments; the input and output pins are fixed. I would like to ask how to modify the code or change software settings to make the fitter pass in this situation. For example, how should I resolve the following error?

    Info (170138): Failed to route the following 2 signal(s)
    Info (170139): Signal "tic:tic0|Add3~1"
    Info (170139): Signal "tic:tic0|WideOr2~2"

    Info (170140): Cannot fit design in device -- following 2 routing resource(s) needed by more than one signal during the last fitting attempt
    Info (170141): Routing resource LAB Input (X48_Y30, I17)
    Info (170141): Routing resource LAB Input (X48_Y30, I48)