Forum Discussion
Altera_Forum
Honored Contributor
13 years agoRegarding the delay I would suggest something like:
P1: PROCESS (clk_in) BEGIN if (delay_cnt_A < xyz) then clk_out_a <= '0'; delay_cnt_A <= delay_cnt_A+1; else clk_out_a <= clk_in; end if; ... END PROCESS; END behav Thus the clk_out_a is constant until the delay_cnt_A has reached the configured "xzy" threshold, i.e. the configured number of clk_in cycles are elapsed... (Just as a rough idea of implementation...)