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My purpose is to design various types of memory with different control mechanisms so I can measure their power and performance. I know there is a built-in memory option in almost any FPGA, but what I need is to build a memory from scratch.
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The problem with this approach is that there is no option to "build a memory from scratch".
You can describe a memory in VHDL or Verilog, and the synthesis tool will implement it using either built-in memory or using logic cells.
If you want to look at performance and power, then you need to use the timing analysis and power analysis tools for a specific test, eg., for power consumption create a design with lots of toggling registers, create a VCD file in Modelsim and then run that through the quartus power analysis tool. For timing analysis, create a design, add timing constraints, and then run a timequest analysis.
Cheers,
Dave
Honored Contributor
