Where is the PWM core/ip?

Perhaps there isn't much call for PWM in the FPGA world? People that need pwm typically use micro-controllers. Even so, I'd be there are PWM impleemntations on opencores.org Try http://opencores.org/project,pwm it is marked done.

An IP core for a PWM? What is this world coming to? Some functions are so simple that an IP core makes no sense. PWM definitely falls into that category IMO.

module pwmGenerator# (
    parameter CTR_WIDTH = 10 //Width of PWM counter
)(
    input clock,
    input reset,
    input tick,   //Clock enable - to divide clock frequency as needed
    input  duty,
   
    output reg pwmOut
);
localparam ZERO = 0;
localparam ONE = 1;
reg  pwmCntr;
always @ (posedge clock or posedge reset) begin
    if (reset) begin
        pwmCntr <= ZERO;
    end else if (tick) begin
        pwmCntr <= pwmCntr + ONE;
    end
end
always @ (posedge clock) begin
   pwmOut <= (pwmCntr < duty);
end

A Verilog implementation of the PWM was already provided on this forum, with the advantage to have the interface that allow you can build your own customized SOPC module to add it on Qsys such as you would do with a standard module, see that: