module pwmGenerator# (
parameter CTR_WIDTH = 10 //Width of PWM counter
)(
input clock,
input reset,
input tick, //Clock enable - to divide clock frequency as needed
input duty,
output reg pwmOut
);
localparam ZERO = 0;
localparam ONE = 1;
reg pwmCntr;
always @ (posedge clock or posedge reset) begin
if (reset) begin
pwmCntr <= ZERO;
end else if (tick) begin
pwmCntr <= pwmCntr + ONE;
end
end
always @ (posedge clock) begin
pwmOut <= (pwmCntr < duty);
end
That took all of 5 minutes to write... - it would have been faster for you to have just written some HDL to do the job than the time you spent searching Quartus for such a simply design and then write this question and wait for answer.
Honored Contributor
