When does power supply ramp time period starts on Stratix IV?

From the Stratix IV handbook:

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When power is applied to a Stratix IV device, a POR event occurs if the power supply reaches the recommended operating range within the maximum power supply ramp time (tRAMP). If tRAMP is not met, the device I/O pins and programming registers remain tri-stated, during which device configuration could fail. The maximum tRAMP for Stratix IV devices is 100 ms; the minimum tRAMP is 50 µs. When the PORSEL pin is high, the maximum tRAMP for Stratix IV devices is 4 ms.

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My question is when exactly does FPGA start counting tRAMP and when does is end counting tRAMP?

My guess is that the start point is when any on the monitored voltages (VCC, VCCAUX, VCCPD, VCCPGM, VCCPT) start ramping-up from the 0V and the end point is when all of the monitored voltages are not ramping-up any more. But how does FPGA know if the monitored voltage has finished ramping-up? Again, my guess is it's when the voltage stays on the same level for some time. Perhaps this is the reason why Altera strictly requires monitored voltages to ramp-up monothonically.

Are my assumptions correct?