Forum Discussion
Altera_Forum
Honored Contributor
17 years agoSharing PLLs is basically possible for LVDS transmitter and receiver using the same reference clock. It doesn't work e. g. for receiver with individual reference clock in source synchronous operation.
Normally a LVDS transmitter or receiver (or a group of channels with common clock) needs a slow (frame) clock and fast (bit) clock. Cause a PLL has five outputs, also two different phased LVDS clock pairs can be provided by one PLL. I'm not sure about the options when let the Megawizard automaticly configure shared PLLs, but it would be possible in external PLL mode.