Altera_Forum
Honored Contributor
Honored ContributorWhat's the suggested DDR3 memory layout for Cyclone V?
Hello,
Cyclone V hard- or software DDR3 controller don't support write leveling, so a "flyby" address and clock line topology can't be implemented due to too high delay skew. For the same reason, industry standard DDR3 DIMM modules can't be used with Cyclone V. DDR3 memory designs are required to use discrete memory chips instead. The external memory interface handbook tells: --- Quote Start --- However, when you are designing the DDR3 SDRAM interface using discrete SDRAM components, you may desire a layout scheme that is different than the DIMM specification. You have the following two options: Mimic the standard DDR3 SDRAM DIMM, using a fly-by topology for the memory clocks, address, and command signals. This options needs read and write leveling, so you must use the UniPHY IP with leveling. Mimic a standard DDR2 SDRAM DIMM, using a balanced (symmetrical) tree-type topology for the memory clocks, address, and command signals. Using this topology results in unwanted stubs on the command, address, and clock, which degrades signal integrity and limits the performance of the DDR3 SDRAM interface. --- Quote End --- Obviously, only the second (bad) option is available for Cyclone V DDR3 designs. The interesting question is, if the memory speeds held out in prospect by the Cyclone V hardware manual and the external memory interface spec estimator (400 MHz with C6/C7, 333 MHz with C8) can be actually achieved? And how a reasonable PCB layout connecting recent 4Gb x8 chips in balanced tree topology to a Cyclone V hardware DDR3 interface looks like? Best regards, Frank
