What is Timing between nCEO and DCLK in a multi-device AS Configuration ?

Is there timing requirements between nCEO and DCLK when configuring two FPGA's from one EPCS device?

The master device (the first FPGA configured) operates in an AS configuration mode and once configured

pulls down the nCEO output connected to the nCE pin of the next FPGA to be configured. The DCLK does

runs continuously through the point where nCEO transitions to low.

The FPGA's are Cyclone III's.

The online documentation for configuring Cyclone III's discusses using the PS mode to configure multiple

FPGA's in the context of using a MAX II or a processor. It states:

"After the first device completes configuration in a multi-device configuration chain, its nCEO pin drives low to activate the nCE pin of the second device, which

prompts the second device to begin configuration. The second device in the chain

begins configuration in one clock cycle."

Configuration begins in one clock cycle, it says, but is it OK to be off by a clock after nCEO goes low?

DCLK to the second FPGA has a delay of 5.5 ns with respect to nCEO because DCLK is buffered before

being routed to the second FPGA.

Does the bitstream have padding at the start of the second FPGA configuration and use a "Start" indication

before clocking in the configuration bits? This would avoid issues with the nCEO/DCLK timing.

Currently my second FPGA is not configuring correctly and allowing Config_Done.