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The problem has been resolved. My expensive PCB layout tool was not supposed to let me cross my signals, but some how it did. DATA0 and DCLK on the FPGA that would not configure were swapped on the PCB but not on the schematic. Its over. I can get on with the project and my life again.
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Can you elaborate on this a little more.
I have PCB tools from Mentor and Cadence, and have never seen this issue (other than a user-mistake in the schematic).
Can you check that when you netlist the schematic design, and import that netlist into your PCB design that you get no net changes? It sounds more like a case that the error was fixed in the schematic after the PCB was built. Though if you were the designer of both the schematic and PCB, and you do not recall doing that, then we'll have to think of another hypothesis :)
I'm glad to hear you resolved the issue, however, the cause still sounds a little scary ...
Cheers,
Dave
Honored Contributor
