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Honored Contributor
Honored ContributorWhat is Timing between nCEO and DCLK in a multi-device AS Configuration ?
Is there timing requirements between nCEO and DCLK when configuring two FPGA's from one EPCS device? The master device (the first FPGA configured) operates in an AS configuration mode and once ...
Altera_ForumHonored Contributor
Honored ContributorClarifications:
The 3rd Board was previously not available to test this FPGA configuration issue with because of a bad power regulator. The regulator was fixed and I am able to power the board and attempt to program the FPGA's on it. If it did not have the problems the other boards had I would have replaced the FPGA's on the first two boards. I am about to concede to trying to configure the FPGA's from something other than the EPCS with pof's. I have an alternate set of DATA0, DCLK, nCE, etc. signals routed from another (well behaved) FPGA on the board. So I concatenate my two *.rbf's and clock these bytes in serially. So do you have a reference for the details of doing this ? Is the serial stream MSB first ? Do I need to do any byte swapping things?
