Forum Discussion
3 Replies
- NurAiman_M_Intel
Super Contributor
Hi,
Thank you for contacting Intel community.
Have you follow MAX 10 configuration userguide? If not, please kindly refer to the userguide below:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf#page=28
Let me know if you need further information.
Thank you.
Regards,
Aiman
- zlan01
New Contributor
thanks a lot for you help,
after powering on, the fpga will:
- be configured by the configuring file
- after being configured , reset the whole register,
- go to implement the function
the content you mentioned above is the work in phase 1 , and what I care about is in phase 2 above,
- firstly can I use locked of the pll to reset the register of the fpga as below:
assign reset = locked ?
2. secondly , or should I construct a Resistance capacitance charging circuit to get the reset signal , and then input the reset signal to the FPGA ?
what is the best mode to reset the fpga register ?
- NurAiman_M_Intel
Super Contributor
Hi,
- You can perform reset by using PLL or reset IP.
- You can also write RTL to perform reset internally when there is some problem
or you can connect the reset input to a switch
depends on your design.
Thank you.
Regards,
Aiman