What is the processing speed limitation of Cyclone IV E with speed grade C7?

Hi Michael,

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My eyes just went numb from this point

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Ha!

A picture is worth a thousand words ...

http://www.ovro.caltech.edu/~dwh/carma_board/digitizer_tests.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/digitizer_tests.pdf)

p64: the top trace is the 'frame clock' the bottom is serialized data.

p71 and on explain the receiver deserializer and framing.

Try to redraw the figures on p73 and 74 for your case. For example, for every period of your 60MHz frame clock, you diagrams would have 12-bits of serialized data. However, since the LVDS receiver would be configured in 6-bit mode, you would get a parallel output word every half frame clock (my diagrams don't show the parallel data inside the FPGA, but yours could).

Once you can draw a figure, your eyes will become less numb :)

Cheers,

Dave