What is the processing speed limitation of Cyclone IV E with speed grade C7?

Dave,

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Even if your 60MHz data is aligned perfectly with your 12-bit ADC data, you'll have to work out how to pack your 6-bit data into the recovered ADC 12-bit samples. One way I can think of is that your 120MHz receive clock can use the 60MHz frame clock, eg., the 12-bit data will be 2 x 6-bits of data, and the first 6-bit value will occur when the frame clock is high, and the second when the frame clock is low (relative to the 120MHz receive clock). Actually, with this scheme, you would not use dual-ported RAM with different port widths to capture data, you'd just use a 12-bit receive register clocked at 120MHz; the frame clock would be used as a low/high 6-bit enable, and at every high clock (after a complete 12-bits was updated in the register), you would write to a 12-bit dual-clock FIFO. The FIFO would be clocked at 120MHz on one side, and be written every second clock with 12-bits, while the other side of the FIFO would be clocked at 60MHz and read every clock.

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My eyes just went numb from this point, anyway. Thank you very much, this is very helpful. I will try my best to understand it, and if i get stuck again, i will post some questions here.

Thanks!

Michael