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Altera_Forum
Honored Contributor
Honored ContributorWhat is the processing speed limitation of Cyclone IV E with speed grade C7?
Hi everyone, Does anyone know, what is the maximum processing speed of Cyclone IV E (with speed grade of C7) within the FPGA fabric? Knowing that PLL on Cyclone IV E can generate up to 1....
Altera_ForumHonored Contributor
Honored ContributorHi,
IIRC, although the dropbox only shows "10", I think you can type in 12 to generate a altlvds_rx core with a deserialization factor of 12. If that doesn't work out, you'll have to write out your own deserializer -- search this forum, I think there are code snippets arround. In Verilog (or VHDL), you just use the "p" signal and let the tools automatically create the "_n" signal. That is, in your Verilog, you only need a "HSMC_RX_D" signal. When you assign that signal as LVDS, the fitter will automatically create a "HSMC_RX_D_n" signal.
