What is the processing speed limitation of Cyclone IV E with speed grade C7?

Dave,

I just happens to see your latest post when i check back all my previous post, i am not sure why i didn't get a notification via email.

Anyway, thanks for all these information, its very helpful.

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What are you trying to do with the AFE? Ultrasonic beamforming for medical, NDT, sonar?

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This is our college senior design project, i am majoring in Electrical engineering in a bachelor degree, but our professor just choose an extremely challenging project for us, personally i haven't have much experience on FPGA, we only have 2 classes with CPLD.

This AFE5808 from TI will be used on a pig's heart for researching in Shearwave Dispersion Ultrasound Vibrometry (SDUV) imaging.

I have a new question, and this is quite critical and urgent, i would be really grateful if someone shed some light for me.... alright here's the scenario;

A LVDS stream(12 bit * 60 MHz = 720Mbps) is coming to my FPGA from an ADC, since it is in 12 bits and it is transmitted throught 2 wires (which means 1 channel? am i right), how can i ultilize the ALTLVDS_RX megacore provided by Altera (since the maximum deserialization factor selectable is just 10) to do deserialization ?? should i use 2 channel(in the parameterized core settings) and input HSMC_RX_D_P[0] to one of the pin while, HSMC_RX_D_N[0] to the other input?? or is there a trick of doing this? If i have to write my own shift register code, how should i address differential signalling in verilog? should i just consider " HSMC_RX_D_P[0]" and never have to consider "HSMC_RX_D_N[0]", since they are just 180 degree out of phase or the inverse of each other.

Michael