Honored Contributor
Honored ContributorHi Michael,
--- Quote Start --- I've always wanted to ask what's the difference between MHz and Mbps in LVDS? Since LVDS is basically in binary, which is on and off per unit time, so i thought using MHz to describe Mbps here would be the same? --- Quote End --- There's often a factor of two between MHz and Mbps. Eg., look at connector specifications from Samtec (makers of HSMC connectors). They will specify connectors at eg. 9GHz or 18Gbps. If I have a clock at say 100MHz, the fastest I can toggle a signal using the rising edge is 100Mbps. However, as the other poster commented, using both the rising and falling edges of the clock, you can get two bit toggles per time period, so 200Mbps, twice the clock frequency. In the case of the 740Mbps LVDS, the 'clock' is 370MHz DDR. --- Quote Start --- Could you elaborate a little more on how you get 105MHz?, and what is setup/hold time of the receivers? --- Quote End --- If your ADC is 14-bits at 50MHz, then the serialized data rate is 50*14 = 700Mbps. If you receive that via LVDS, with the receiver in x7 mode, then the data will be deserialized inside the FPGA as 7-bits every 100MHz. You would then need to wait for the next 7-bit sample from the LVDS receiver before you had the 14-bits you need for processing. I'm not sure what the setup and hold time of the receivers is. Timequest will tell you. Create an LVDS design and perform a timing analysis. --- Quote Start --- "Adding an external clocked multiplexer..." i wanted to make this in the FPGA using verilog. If this does not work, do you think it will work if i use a discrete deserializer chip? --- Quote End --- Its not worth thinking about this route. The best solution is an FPGA. It just happens that you can't run your ADC at 65MHz. You haven't indicated that running it at 50MHz is a problem. Is it? --- Quote Start --- And how could one overclocks the FPGA? cool down the FPGA? increase core voltage? this is getting interesting!. --- Quote End --- Initially, you'd try to lie :) You compile the project for the highest speed grade device and see if the design meets timing. If it does, then you download it to your board and see if it works. If it doesn't, then, I guess, try changing the temperature. The other way to overclock is to control the clocks. The Altera ALTPLL megafunctions you use in the design will be automatically configured by your selections in GUIs. You can however, control all the PLL parameters directly using the ALTPLL_RECONFIG function, so you use that to increase the receiver frequency until things break. Controlling the PLL phase is very useful. It allows you to slide the FPGA clock closer to the edges of the receiver eye patterns, and from that you can determine how much timing margin you have. Eg. you could determine whether 910Mbps is possible while running your design at 700Mbps. How many channels of ADC do you need? Another scheme you may not have thought of, is to operate the ADCs out-of-phase by 180-degrees, eg. by using an inverted clock. I did not look at the device data sheet to see whether this was a feature, but perhaps you could use two ADCs per analog signal. Then you could interface to each ADC at 50MHz, yet be sampling the signal effectively at 100MHz. Inside your FPGA, you would take the 14-bit samples from each FPGA and interlace them to create the effective 100MHz ADC. That is the theory anyway, in practice you might have to initialize the system to get the clock phases and the channel gains correct. Depending on how many bits you really need, it might be ok. What are you trying to do with the AFE? Ultrasonic beamforming for medical, NDT, sonar? Cheers, Dave
