What is the difference between these two clear signals?

Hi, I’m currently investigating an issue. I’m using an FPGA SCFIFO to replace a 72V251 FIFO, with rclk = wclk.

I found that if I keep rebooting the device, my industrial camera occasionally shows image tearing. However, this does not happen every time, and my pixel clock is only 36 MHz, so I would not consider it a very high frequency.

Could I ask what the difference is between these two FIFO reset options?

• Asynchronous clear
• Synchronous clear (flush the FIFO)