What is the default I/O termination impedance on a Stratix III FPGA?

I am routing a 60MHz clock signal to one of the output pins on chip(not through a clk dedicated pin,just a normal I/O pin), and need to know the output impedance to match the trace impedance.

What is the default I/O termination resistance on Stratix III if OCT is not enabled. The handbook doesn’t explicitly say it.

Is 50ohm OCT normally suggested in this case? Or a series resistor can be added (but the default output resistance still needs to be known…), I read an application note about it which uses a SI EDA (the EDA has the FPGA I/O resistance in its library)to calculate the series resistor value.